MITRE Common Interface for Register Transfer Level Models Using Open Core Protocol Profiles

This document describes a set of standard interfaces for register transfer level (RTL) blocks developed at MITRE. The interfaces leverage the industry standard Open Core Protocol (OCP) to define the connections between blocks. The interfaces are only intended to describe the connections between blocks, not connections external to a device (e.g. field programmable gate array (FPGA) or application specific integrated circuit (ASIC). The initial focus of these interfaces is on blocks which generate, manipulate or route data samples through the platform. The exact definition of a block is purposely left vague since it will vary with the application. Having a common interface structure simplifies reuse and compatibility of blocks between projects.