Details of the decoder implementation, including memory layout, parallelization architecture, layered-decoding scheduling, and field programmable gate array (FPGA) resource utilization are presented.
Implementing the NASA Deep Space LDPC Codes for Defense Applications
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Selected codes from, and extended from, the NASA's deep space low-density parity-check (LDPC) codes are implemented for high speed defense applications. This is part of an effort to build Government reference waveform implementations to assist defense acquisition programs and to promote waveform re-use. Details of the decoder implementation, including memory layout, parallelization architecture, layered-decoding scheduling, and field programmable gate array (FPGA) resource utilization are presented.