DirAc: An Integrated Circuit for Direct Acquisition of the M-Code Signal

This paper describes the first integrated circuit (IC) designed, fabricated, and tested to perform direct acquisition of the M code signal. This DirAc IC prototype provides direct acquisition capability for test receivers and also demonstrates the feasibility of performing direct acquisition over extended regions of time and frequency uncertainty. The IC is designed and fabricated using 180 nm technology, and has been tested to demonstrate complete functionality and full performance. It uses parallel code matched filters, with FFT-based backend processing to search over 800 Hz of frequency uncertainty and 10 msec of time uncertainty in parallel, using off-chip memory for noncoherent integration. Multiple such time-frequency tiles are searched serially. Inputs are sampled at 2 bits each inphase and quadraphase. The DirAc IC supports a maximum integration time (combined coherent and noncoherent integration) of 1.28 seconds, and includes compensation for code Doppler. Coherent integration time up to 10 msec can be used. The DirAc IC's architecture takes advantage of the M-code signal's binary offset carrier (BOC) modulation to reduce acquisition processing complexity. DirAc supports different modes and features of the M-code signal. Hardware is time-shared between inphase and quadraphase processing and also between upper and lower sidebands of the BOC modulation. The architecture uses a pipelined design to provide the equivalent processing capability of 3.2 million parallel correlators, performing 2 tera operations per second. Average power consumption in a typical application is less than 1 mW. The IC design and layout process are also described, identifying techniques used to efficiently design and layout the IC. Theoretical predictions are provided for search speed and for the ability to work at different levels of carrier-to-noise density ratio.