Today's complex datapath architectures for System-on-a-Chip (SoC) and FPGA-based systems demand more effective verification techniques to reduce cost and schedule risks.
The Diagnostic Channel: Increasing Visibility and Control in SystemC Models
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Today's complex datapath architectures for System-on-a-Chip (SoC) and FPGA-based systems demand more effective verification techniques to reduce cost and schedule risks. Typical transaction-level-modeling techniques, when used for verification, lack in observability and controllability of internal states and signals. We introduced a novel approach to the functional verification of datapath systems by embedding diagnostic channel testbench components throughout the design. Diagnostic channels differ from traditional SystemC channels because they can verify and generate data as well as bind to multiple input and output ports. A brief case study using the diagnostic channels is presented along with plans for future work.